Rowdie Rooster's CSCE430 Course Project WikiEdit

This is the wiki page describing team Rowdie Rooster's computer architecture course project.  The project consists of building a pipelined RISC processor that has hardware-based data hazard resolution mechanics, a static branch predictor, and set-associative instruction/data caches.


Jackson Dinh

Courtney Ingersoll

Jake Schmitt

Travis Sweetser

University of Nebraska - Lincoln

Computer Architecture (CSCE430)

Dr. Lei Tian

Fall 2013

Project OverviewEdit

The project consists of building a pipelined RISC processor to solve for the greatest common factor (GCF) between two or more integers.  The project is divided into four tasks.  Task 1 involves defining a instruction set architecture (ISA) for our processor, and writing a two-pass assembler to set up the instruction memory and the data memory separately.  Task 2 is to partition our processor into pipelined stages.  This task also involves creating hardware-based data hazard resolution mechanisms.  Task 3 is creating a static branch predictor within our processor.  Finally, Task 4 is adding two set-associative caches, one for data and one for instructions.  The project also involves maintaining this wiki, writing a final report fully describing our design, demonstrating our processor, and giving a brief presentation.

Table of ContentsEdit

Task 1: RISC ISA and Assembler

Task 2: Pipelining

Task 3: Static Branch Predictor

Task 4: Instruction & Data Caches

Team Information


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