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This section tracks all information relating to the team and extra resources.  This includes each team member's roles and duties in the project, our project progress, and external project resources.



Team DutiesEdit

This section gives some basic information on each team member, and gives credit to their main contributions.  Overall, the project was very well balanced between each group member.


TeamPic

Team Rowdie Roosters. Jack Schmitt (back left), Jackson Dinh (back right), Travis Sweetser (front left), and Courtney Ingersoll (front right).















Jake SchmittEdit

JakeSchmitt

Jake Schmitt



  • Team Leader
  • Major: Computer Engineering
  • Senior Undergraduate
  • Main Contributions to Project:
    • led Task 1: RISC ISA & Assembler
    • programmed assembler
    • main project verification


Jackson DinhEdit

JacksonDinh

Jackson Dinh




  • Major: Computer Science
  • Senior Undergraduate
  • Main Contributions to Project
    • led Task 2: Pipelining - Forwarding
    • co-main project debugging
    • main project research


Travis SweetserEdit

TravisSweetser

Travis Sweetser




  • Major: Computer Engineering
  • Senior Undergraduate
  • Main Contributions to Project:
    • led Task 2: Pipelining - Data Hazards
    • led Task 3: Static Branch Predictor
    • co-main project debugging
    • defined ISA


Courtney IngersollEdit

CourtneyIngersoll

Courtney Ingersoll




  • Majors: Computer Engineering & Electrical Engineering
  • Senior Undergraduate
  • Main Contributions to Project:
    • led Task 4: Instruction & Data Caches
    • main wiki updating
    • main project documentation

Extra DocumentationEdit

In addition to our wiki, we were also required to write a formal report on our project and present our design.


Final ReportEdit

Our project report can be viewed here: https://docs.google.com/document/d/1lgL6JbjvVzvVx0K0yUlLYCP3U9av8Wk3Nbn2KzGe3vQ/edit?usp=sharing


PowerPoint PresentationEdit

Our project presentation can be viewed here: https://docs.google.com/presentation/d/1ViA0sfqChIYvsq2Rn-E-zrLIqZfmzhDL4StDo8qWpX0/edit?usp=sharing


Project ProgressEdit

<Though we had just about the whole semester to work on this project, we procrastinated.  The most notable progress made to this project happened only in the last 3 weeks.  We will come back to formally write out our progress schedule during that time when we are able. Thank you for your patience.>

Additional ResourcesEdit

These were additional published works, outside of our professor's lectures, that our team referenced while designing our processor.


WebsitesEdit

Quartus Pin Assignments: ftp://ftp.altera.com/up/pub/Altera_Material/12.1/Boards/DE2/DE2.qsf

Greatest Common Divisor Programming Examples:http://rosettacode.org/wiki/Greatest_common_divisor

Programming Language Parser Generator: http://www.antlr.org/


Written WorksEdit

Computer Architecture: A Quantitative Approach by John L. Hennessy and David A. Patterson (5th ed.)

  • ISBN-10: 01238387X
  • ISBN-13: 978-012383728

Cache Design (PowerPoint Lecture) by Dr. Michael B. Taylor: http://cseweb.ucsd.edu/classes/fa10/cse240a/pdf/08/CSE240A-MBT-L15-Cache.ppt.pdf


MLA CitationsEdit

Altera Corporation. Quartus II. Pin Assignment Documentation. Altera.com. Altera Corporation, 2010. Web. 9 Dec. 2013. <ftp://ftp.altera.com/up/pub/Altera_Material/12.1/Boards/DE2/DE2.qsf>.

"Greatest Common Divisor." Rosetta Code. Michael Mol, 13 Nov. 2013. Web. 9 Dec. 2013. <http://rosettacode.org/wiki/Greatest_common_divisor>.

Hennessy, John L. and David Patterson. Computer Architecture: A Quantitative Apprach. 5th ed. Amsterdam: Elsevier, 2012. Print.

Parr, Terence. Antlr. Computer software. Antlr, Vers. 3. ANTLR / Terence Parr, 2012. Web. 9 Dec. 2013. <http://www.antlr.org/>.

Taylor, Michael B., Dr. "Cache Design." Graduate Computer Architecture. San Dieago, CA. The University of California. 11 Nov. 2010. Web. <http://cseweb.ucsd.edu/classes/fa10/cse240a/pdf/08/CSE240A-MBT-L15-Cache.ppt.pdf>.

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